This invention relates, in general, to semiconductor devices and to their fabrication, and more particularly, to a vertically oriented EEPROM device, and to a method of fabrication.
State of the art electrically-erasable-programmable-read-only-memory (EEPROM) devices having a split-gate configuration offer increased programming efficiency, and can be operated with a single, low-voltage power supply. Typically, an EEPROM device includes a field-effect-transistor (FET) formed in a silicon substrate. The FET includes a floating gate electrode overlying a semiconductor substrate. Electrical charge is transferred to the floating gate electrode through a tunnel dielectric layer, which separates the floating gate electrode from the semiconductor substrate. A control gate electrode is capacitively coupled to the floating gate electrode, such that a voltage applied on the control gate electrode is coupled to the floating gate electrode. Charge transfer to the floating gate electrode is initiated by coupling the voltage from the control gate electrode to the floating gate electrode.
In the split-gate configuration, a select gate electrode also overlies a portion of the channel region of the FET adjacent to the floating gate electrode. The select gate electrode regulates the electrical current flowing in the channel region during programming, at which time the charge is placed on the floating gate electrode. When the select gate electrode is positioned adjacent to the source region in the FET, the EEPROM transistor can be programmed by source-side injection. During programming, an electric field gradient is established in the channel region of the FET, such that electrons originating in the source region are accelerated across a potential drop, and are injected into a floating gate electrode. Programming by source-side injection is carried out at low current levels, which permits EEPROM transistors to be programmed by charge pumping from a single, low-voltage power supply.
While the use of a split-gate configuration and an EEPROM device provides improved device performance, the necessity of placing three gate electrodes in close proximity requires that the EEPROM transistor consume a substantial amount of substrate surface area. More efficient utilization of substrate surface area in advance memory technology is a prominent objective in order to increase the density and the number of memory cells. Conventionally, split-gate EEPROM transistors have been formed in a semiconductor substrate by creating a horizontally disposed channel region intermediate to a source region and a drain region. The floating gate electrode is also horizontally disposed over the channel region. The control gate electrode and the select gate electrode are then positioned about the floating gate electrode. Generally, the floating gate electrode and the control gate electrode are also substantially horizontally disposed on the substrate surface. The necessity of placing the select gate electrode and the floating gate electrode on a horizontally disposed channel region consumes a large amount of substrate surface area.
More recently, split-gate EEPROM transistors have been constructed within trenches formed within a semiconductor substrate. The floating gate electrode, select gate electrode and control gate electrodes are placed within the trench, and the channel region of the FET resides in the substrate along the wall of the trench. Placement of the gate electrodes within the confines of a trench substantially reduces the amount of substrate surface area necessary to form an EEPROM transistor. While placing the gate electrodes of an EEPROM transistor in a trench reduces consumption of substrate surface area, it can be difficult to make electrical contact to the gate electrodes within the trench.
In other applications, more conventional dual-gate EEPROM transistors have been developed that arrange a floating gate and a control gate about a central pillar extending vertically from the semiconductor substrate. Although the pillar arrangement enables control gate electrodes and bit lines to be arranged such that they can be easily contacted in a memory array, the pillar designs cannot obtain the advantages of source-side injection and low-voltage cell operation in the absence of a select gate electrode. Accordingly, further development work is necessary in the design of the EEPROM transistors to provide non-volatile memory devices that can be formed in high density cell arrays, and that can be operated with a single, low-voltage power supply.
In practicing the present invention there is provided a split-gate vertically oriented EEPROM device, which achieves operational efficiency by arranging a select gate electrode, a floating gate electrode, and a control gate electrode about a central, vertically disposed channel region. In one embodiment of the invention, a semiconductor substrate is provided having a vertically disposed semiconductor body thereon. A doped region in the substrate separates the vertically disposed semiconductor body from the substrate. A horizontally disposed gate electrode overlies the substrate adjacent to the vertically disposed semiconductor body. A first vertically disposed gate electrode overlies the horizontally disposed gate electrode and is positioned adjacent to the vertically disposed semiconductor body. The horizontally disposed gate electrode regulates the flow of electrical charge into the vertically disposed semiconductor body from the semiconductor substrate.
An EEPROM device arranged in accordance with the invention, enables the formation of an EEPROM memory array using field-plate isolation eliminating the need for field isolation regions within the semiconductor substrate. Additionally, an EEPROM. device formed in accordance with the invention, can be operated from a single, low-voltage power supply and programmed by source-side-injection.